1
1668mib
Gast
Hallo,
ich habe einen i5-2390T gekauft und der läuft in einem ASRock Z68 Pro3. Das Betriebssystem ist Windows Server 2008 R2 und es wird die Rolle HyperV zur Virtualisierung genutzt.
Ausschlag für den Kauf der CPU gaben vor allem die Instructions der CPU. Allerdings sind laut CPU-Z, AIDA64 und dem Tool coreinfo nicht alle Befehlssätze nutzbar, allen voran AES-NI fehlt. In den UEFI-Einstellungen sehe ich auch keinen entsprechenden Punkt.
VMX sollte eigentlich auch möglich sein, im UEFI sind beide entsprechenden VT-Punkte aktiivert.
Die Firmware des Mainboards sollte mit 1.60 die aktuelle sein.
Jemand eine Ahnung, warum die Befehlssätze nicht zur Verfügung stehen?
coreinfo Ausgabe:
ich habe einen i5-2390T gekauft und der läuft in einem ASRock Z68 Pro3. Das Betriebssystem ist Windows Server 2008 R2 und es wird die Rolle HyperV zur Virtualisierung genutzt.
Ausschlag für den Kauf der CPU gaben vor allem die Instructions der CPU. Allerdings sind laut CPU-Z, AIDA64 und dem Tool coreinfo nicht alle Befehlssätze nutzbar, allen voran AES-NI fehlt. In den UEFI-Einstellungen sehe ich auch keinen entsprechenden Punkt.
VMX sollte eigentlich auch möglich sein, im UEFI sind beide entsprechenden VT-Punkte aktiivert.
Die Firmware des Mainboards sollte mit 1.60 die aktuelle sein.
Jemand eine Ahnung, warum die Befehlssätze nicht zur Verfügung stehen?
coreinfo Ausgabe:
Intel(R) Core(TM) i5-2390T CPU @ 2.70GHz
Intel64 Family 6 Model 42 Stepping 7, GenuineIntel
HTT - Hyperthreading enabled
HYPERVISOR * Hypervisor is present
VMX - Supports Intel hardware-assisted virtualization
SVM - Supports AMD hardware-assisted virtualization
EM64T * Supports 64-bit mode
SMX - Supports Intel trusted execution
SKINIT - Supports AMD SKINIT
EIST * Supports Enhanced Intel Speedstep
NX * Supports no-execute page protection
PAGE1GB - Supports 1GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4-MB pages
PSE36 * Supports > 32-bit address 4-MB pages
PGE * Supports global bit in page tables
SS * Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
FPU * Implements i387 FP instructions
MMX * Supports MMX instruction set
MMXEXT - Implements AMD MMX extensions
3DNOW - Supports 3DNow! instructions
3DNOWEXT - Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 * Supports Streaming SIMD Extensions 3
SSSE3 * Supports Supplemental SIMD Extensions 3
SSE4.1 * Supports Streaming SIMD Extensions 4.1
SSE4.2 * Supports Streaming SIMD Extensions 4.2
AES - Supports AES extensions
AVX * Supports AVX intruction extensions
FMA - Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTTR * Supports Memory Type Range Registers
XSAVE * Supports XSAVE/XRSTOR instructions
OSXSAVE * Supports XSETBV/XGETBV instructions
CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 * Supprots CMPXCHG16B instruction
DCA - Supports prefetch from memory-mapped device
F16C - Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR - Supports optimized FXSAVE/FSRSTOR instruction
MONITOR - Supports MONITOR and MWAIT isntructions
MOVBE - Supports MOVBE instruction
PCLULDQ - Supports PCLMULDQ instruction
POPCNT * Supports POPCNT instruction
SEP * Supports fast system call instructions
DE * Supports I/O breakpoints including CR4.DE
DTES64 - Can write history of 64-bit branch addresses
DS - Implements memory-resident debug buffer
DS-CPL - Supports Debug Store feature with CPL
PCID - Supports PCIDs and settable CR4.PCIDE
PDCM - Supports Performance Capabilities MSR
RDTSCP * Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE - Local APIC supports one-shot deadline timer
xTPR * Supports disabling task priority messages
ACPI * Implements MSR for power management
TM * Implements thermal monitor circuitry
TM2 * Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC - Supports x2APIC
CNXT-ID - L1 data cache mode adaptive or BIOS
MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE * Supports use of FERR#/PBE# pin
PSN - Implements 96-bit processor serial number
Logical to Physical Processor Map:
**-- Physical Processor 0 (Hyperthreaded)
--** Physical Processor 1 (Hyperthreaded)
Logical Processor to Socket Map:
**** Socket 0
Logical Processor to NUMA Node Map:
**** NUMA Node 0
Logical Processor to Cache Map:
**-- Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**-- Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**-- Unified Cache 0, Level 2, 256 KB, Assoc 8, LineSize 64
--** Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--** Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--** Unified Cache 1, Level 2, 256 KB, Assoc 8, LineSize 64
**** Unified Cache 2, Level 3, 3 MB, Assoc 12, LineSize 64
Logical Processor to Group Map:
**** Group 0
Intel64 Family 6 Model 42 Stepping 7, GenuineIntel
HTT - Hyperthreading enabled
HYPERVISOR * Hypervisor is present
VMX - Supports Intel hardware-assisted virtualization
SVM - Supports AMD hardware-assisted virtualization
EM64T * Supports 64-bit mode
SMX - Supports Intel trusted execution
SKINIT - Supports AMD SKINIT
EIST * Supports Enhanced Intel Speedstep
NX * Supports no-execute page protection
PAGE1GB - Supports 1GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4-MB pages
PSE36 * Supports > 32-bit address 4-MB pages
PGE * Supports global bit in page tables
SS * Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
FPU * Implements i387 FP instructions
MMX * Supports MMX instruction set
MMXEXT - Implements AMD MMX extensions
3DNOW - Supports 3DNow! instructions
3DNOWEXT - Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 * Supports Streaming SIMD Extensions 3
SSSE3 * Supports Supplemental SIMD Extensions 3
SSE4.1 * Supports Streaming SIMD Extensions 4.1
SSE4.2 * Supports Streaming SIMD Extensions 4.2
AES - Supports AES extensions
AVX * Supports AVX intruction extensions
FMA - Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTTR * Supports Memory Type Range Registers
XSAVE * Supports XSAVE/XRSTOR instructions
OSXSAVE * Supports XSETBV/XGETBV instructions
CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 * Supprots CMPXCHG16B instruction
DCA - Supports prefetch from memory-mapped device
F16C - Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR - Supports optimized FXSAVE/FSRSTOR instruction
MONITOR - Supports MONITOR and MWAIT isntructions
MOVBE - Supports MOVBE instruction
PCLULDQ - Supports PCLMULDQ instruction
POPCNT * Supports POPCNT instruction
SEP * Supports fast system call instructions
DE * Supports I/O breakpoints including CR4.DE
DTES64 - Can write history of 64-bit branch addresses
DS - Implements memory-resident debug buffer
DS-CPL - Supports Debug Store feature with CPL
PCID - Supports PCIDs and settable CR4.PCIDE
PDCM - Supports Performance Capabilities MSR
RDTSCP * Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE - Local APIC supports one-shot deadline timer
xTPR * Supports disabling task priority messages
ACPI * Implements MSR for power management
TM * Implements thermal monitor circuitry
TM2 * Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC - Supports x2APIC
CNXT-ID - L1 data cache mode adaptive or BIOS
MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE * Supports use of FERR#/PBE# pin
PSN - Implements 96-bit processor serial number
Logical to Physical Processor Map:
**-- Physical Processor 0 (Hyperthreaded)
--** Physical Processor 1 (Hyperthreaded)
Logical Processor to Socket Map:
**** Socket 0
Logical Processor to NUMA Node Map:
**** NUMA Node 0
Logical Processor to Cache Map:
**-- Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**-- Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**-- Unified Cache 0, Level 2, 256 KB, Assoc 8, LineSize 64
--** Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--** Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--** Unified Cache 1, Level 2, 256 KB, Assoc 8, LineSize 64
**** Unified Cache 2, Level 3, 3 MB, Assoc 12, LineSize 64
Logical Processor to Group Map:
**** Group 0
