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Rules of thumb :
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1) 68000 external data bus is 16 bit so any operation on a long word in memory
will take at least 2 full bus cycles.
2) 68000 internal data bus is 32 bit so reading/writing word or long word from
/ to a register take the same time.
3) There are 3 math units. One 16 bit ALU and two 16 bit Address Units. The ALU
was complex enough for the math instruction set while the AUs were only able to
do address related math (add, subtract).
So, The ALU is used in the execution of instructions whereas the AUs are used
to calculate the effective address(es). And, of course, the 2 16 bit AUs worked
together to make the 32 bit effective address calculations.
Therefore, to do a simple 16 bit math instruction, the ALU can do the operation
while the AUs perform address calculations during the same micro-cycle.
3a) 68000 ALU is 16 bits so any arithmetic or logic operation between 2 values
take more cycles with long words values than with words values even if source
and destination are registers.
3b) For arithmetic operations on an address register such as ADDA and SUBA, the
whole 32 bits destination address register is used regardless of the operation
size (.W or .L). As this arithmetic operation is done by the ALU and no the AUs
and in regard of the previous rule (3a), the ALU will take longer to perform
word sized operations on address registers than on data registers.
4a) in general case, the source operand is evaluated first then the destination
operand is evaluated and, at last, the instruction is executed. These 3 steps
can't be mixed. "addi.w #<data>,-(An)" is a good exemple for this rule.
4b) there are some optimized instructions for which the previous rule doesn't
apply, destination operand evaluation starts before the end of source operand
evaluation. "abcd.b -(Ay),-(Ax)" is a good exemple for this rule.
5) As SP=A7 it seems obvious than (d16,An) and (d16,SP) always have the same
timings. Same thing for (d8,An,Xn) and (d8,SP,Xn).
