wie? na dann hast du aber schon ne menge gelesen.
die quellen hast schließlich auch gelesen?
References
^ Risch, L. "Pushing CMOS Beyond the Roadmap", Proceedings of ESSCIRC, 2005, p. 63
^
http://www.itrs.net/Links/2006Update/FinalToPost/04_PIDS2006Update.pdf Table39b
^ Subramanian V (2010). "Multiple gate field-effect transistors for future CMOS technologies". IETE Technical Review 27: 446–454.
^ Wong, H-S. Chan, K. Taur, Y. "Self-Aligned (Top and Bottom) Double-Gate MOSFET with a 25 nm Thick Silicon Channel" IEDM 1997, p.427
^ Wilson, D.; Hayhurst, R.; Oblea, A.; Parke, S.; Hackler, D. "Flexfet: Independently-Double-Gated SOI Transistor With Variable Vt and 0.5V Operation Achieving Near Ideal Subthreshold Slope" SOI Conference, 2007 IEEE International
^ Huang, X. et al. (1999) "Sub 50-nm FinFET: PMOS" International Electron Devices Meeting Technical Digest, p. 67. December 5–8, 1999.
^ Hisamoto, D. et al. (1991) "Impact of the vertical SOI 'Delta' Structure on Planar Device Technology" IEEE Trans. Electron. Dev. 41 p. 745.
^ Cartwright J (2011). "Intel enters the third dimension". Nature. doi:10.1038/news.2011.274.
^ "Below 22nm, spacers get unconventional: Interview with ASM". ELECTROIQ. Retrieved 2011-05-04.
^ "Intel Reinvents Transistors Using New 3-D Structure". Intel. Retrieved 5/4/2011.
^ a b "Transistors go 3D as Intel re-invents the microchip". Ars Technica. 5 May 2011. Retrieved 7 May 2011.
^ "Intel's New Tri-Gate Ivy Bridge Transistors: 9 Things You Need to Know". PC Magazine. 4 May 2011. Retrieved 7 May 2011.
^ Singh N et al. (2006). "High-Performance fully depleted Silicon Nanowire Gate-All-Around CMOS devices". IEEE Electron Device Letters 27 (5): 383–386. doi:10.1109/LED.2006.873381.
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dann müsstest du eigentlich soviel darüber wissen, dass du n halbes semester vorlesungen darüber geben kannst.
alleine mit dem link und den dazugehörigen quellen wirste zum fachexperten:
http://www.tr.ietejournals.org/arti...ssue=6;spage=446;epage=454;aulast=Subramanian