Ich glaube, die K8 bzw. K10 Architektur braucht sich gegenüber dem Penryn nicht
zu verstecken ... ganz im Gegenteil.
Intel baut erst im kommenden "Nehalem" all die Dinge nach, die bei AMD bereits seit
Jahren für eine fortschrittliche und effziente CPU-Architektur stehen ...
und das mit den Takten wird sich in den kommenden Monaten mit Optimierung
der Fertigungstechnik lösen. Und Performance lässt sich relativ einfach durch größere
Caches optimieren ...
<<< snipp >>
Intel Nehalem Specification Comparison with AMD Core Architecture
Intel is planning to release the next generation processor architecture for the high end PC market by end of 2008. The new core processor architecture is quite different from any of its predecessor even in current Penryn product. Interestingly, some of the features set could be in similarity to
AMD technologies. Known as code name of Nehalem, the actual performance is expected to be much higher as compared to any of the series that exist in today market.
One of great features is the memory controller integration into the silicon die that is believed to be able to boost the whole system performance significantly. An
onboard memory controller will improve the memory access latency as compared to traditional memory access through dedicated bus interface. If you are aware, current AMD core architecture such as K8 already has memory controller being integrated on the silicon level.
Besides this, Nehalem is supported by a high
speed internal bus known as Quick Path Interconnect. It will replace current FSB (
Front Side Bus) in most of the current design. Again, the concept is quite similar to existing HyperTransport technology available in current AMD silicon. Of course they are differences in terms of technology and protocol involved to make them more powerful since Intel is always in leading position with clear roadmap and advanced process technology. On top of these, some of the new features which will be implemented in this silicon are multiple cores with new HT (Hyper-threading) technology,
8MB sharable L3 cache size as well as DDR3 memory support.
Only one drawback, the existing socket design is no longer suitable for use with the new silicon. In other words, it is not backward compatible with current platform in the market and hence OEMs will need to invest more during initial design stage later.
